1. Field of the Invention
The invention relates to memory systems operating with memory devices of varying speeds, and more particularly to determining the particular speeds of the memory devices.
2. Description of the Related Art
Microprocessor-based computer systems have been increasing in performance at a tremendous rate. Much of this increase has been based on the improvements in the microprocessor itself. For example, clock speeds are reaching those previously used only by mainframe computers. However, affordable memory device performance has not been increasing at the same rate. Indeed, dynamic random access memory (DRAM) performance has flattened out recently, with the majority of the effort being concentrated on increasing device storage size. Thus main memory has become a bottleneck.
Cache memory systems, where a small amount of very fast, expensive static RAM is used to store copies of the data, have made the problem somewhat less severe, but the designs are very complicated and expensive. Further, the poor memory performance returns when access must be made to main memory. So there still is a need to improve the performance of the main memory system.
Memory system performance is also a trade off between cost and speed. While conventionally 80 ns DRAMs have been used, 60 ns devices are available, though at a slightly higher cost. While prior memory controllers could utilize differing speeds of DRAMs, allowing the user to make the speed versus cost tradeoff, a mixed speed system did not obtain any benefits. The memory controller could use different speed DRAMs, but only one actual speed of operation was allowed in the system. The memory controller thus ran at the speed of the slowest of the installed DRAMs. This did not allow the user to have fast memory areas, such as the base memory area, and slow memory areas, such as extended memory locations.
One system for mapping memory is described in European Patent Application No. 90 311 749.7, entitled "Data Destination Facility" and published on May 8, 1991, and the counterpart U.S. application, Ser. No. 431,666, filed Nov. 3, 1989, issued on Aug. 23, 1994 as U.S. Pat. No. 5,431,494 which are hereby incorporated by reference. In that system, a data destination facility (DDF) RAM was used for holding address translation, memory module and bank selection, write protect, cacheable status and local memory information. The system upper memory address lines defining 128 kbyte blocks were provided to the DDF RAM as some of the address inputs, with the data being the information. As noted, the system memory address lines only provided a portion of the addressing of the DDF RAM. The upper two bits were provided by two bits previously used to control write protection and remapping and relocation of the BIOS from ROM to RAM. These two bits had previously been located in a specific memory-mapped register. To maintain compatibility with previous software as indicated in the applications, it was thus necessary to set all four possibilities of these two bits and program the DDF RAM for each case. This system, while permitting the remapping of RAM, did not support RAM of differing speeds.
Typically, single in-line memory modules, or SIMMs, are used to provide memory in a modern computer system. These SIMMs provide a four-bit serial identification code to identify both the SIMM size and speed. Reading these identification codes is wellknown in the art, and a technique usable to read the codes is discussed more fully, for example, in U.S. Pat. No. 5,287,531 entitled "Apparatus for System Configuration Determination," issued Feb. 15, 1994, which is hereby incorporated by reference. SIMM size typically ranges from 1 Mb to 64 Mb, with speeds ranging from 100 nanoseconds down to 50 nanoseconds. Unfortunately, there is no standard that is universally accepted to identify these SIMMs. Rather, there are three identification systems that have been used throughout the industry: the "old way," the IBM identification codes, and the JEDEC identification codes. But these identification codes are not the same, and in fact conflict in certain cases. Thus, the identification codes cannot be relied upon to determine memory speed and size, as the SIMMs are otherwise generally interchangeable.
Thus there are memory system performance gains that could be achieved, but conventional design limitations render them only potential, not practical. Therefore it is clearly desirable to have a memory controller which can effectively use different speed memory devices, and to use different speeds, the actual speeds must be determined, and because of the ambiguities discussed above, this cannot be readily done. Thus a way of readily determining SIMM speed is desirable.